1 ? fn9159.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6612a, isl6613a advanced synchronous rectified buck mosfet drivers wi th pre-por ovp the isl6612a and isl6613a are high frequency mosfet drivers specifically designed to drive upper and lower power n-channel mosfets in a synchronous rectified buck converter topology. these drivers combined with hip63xx or isl65xx multi-phase buck pwm controllers and n-channel mosfets form complete core-vol tage regulator solutions for advanced microprocessors. the isl6612a drives the upper gate to 12v, while the lower gate can be independently driven over a range from 5v to 12v. the isl6613a drives both upper and lower gates over a range of 5v to 12v. this drive-voltage provides the flexibility necessary to optimize applications involving trade- offs between gate charge and conduction losses. an advanced adaptive zero shoot-through pr otection is integrated to prevent both the upper and lower mosfets from conducting simultaneously and to minimize the dead time. these products add an overvoltage prot ection feature operational before vcc exceeds its turn-on threshold, at which the phase node is connected to the gate of the low side mosfet (lgate). the ou tput voltage of the converter is then limited by the thres hold of the low side mosfet, which provides some protection to the microprocessor if the upper mosfet(s) is shorted during initial startup. these drivers also feature a three-state pwm input which, working together with intersil?s multi-phase pwm controllers, prevents a negative transient on the output voltage when the output is shut down. this fe ature eliminates the schottky diode that is used in some systems for protecting the load from reversed output voltage events. features ? pin-to-pin compatible with hip6601 soic family ? dual mosfet drives for sy nchronous rectified bridge ? advanced adaptive zero shoot-through protection - body diode detection - auto-zero of r ds(on) conduction offset effect ? adjustable gate voltage (5v to 12v) for optimal efficiency ? 36v internal bootstrap schottky diode ? bootstrap capacitor ov ercharging prevention ? supports high switching frequency (up to 2mhz) - 3a sinking current capability - fast rise/fall times and low propagation delays ? three-state pwm input for output stage shutdown ? three-state pwm input hysteres is for applications with power sequencing requirement ? pre-por overvoltage protection ? vcc undervoltage protection ? expandable bottom copper pad for enhanced heat sinking ? dual flat no-lead (dfn) package - near chip-scale package footprint; improves pcb efficiency and thinner in profile ? pb-free available (rohs compliant) applications ? core regulators for intel? and amd? microprocessors ? high current dc-dc converters ? high frequency and high efficiency vrm and vrd related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? ? technical briefs tb400 and tb417 for power train design, layout guidelines, and feedback compensation design data sheet january 4, 2005
2 fn9159.2 january 4, 2005 ordering information part number** temp. range (c) package pkg. dwg. # isl6612acb 0 to 85 8 ld soic m8.15 isl6612acbz* 0 to 85 8 ld soic (pb-free) m8.15 isl6612acbza* 0 to 85 8 ld soic (pb-free) m8.15 isl6612acr 0 to 85 10 ld 3x3 dfn l10.3x3 isl6612acrz* 0 to 85 10 ld 3x3 dfn (pb-free) l10.3x3 isl6612aecb 0 to 85 8 ld epsoic m8.15b isl6612aecbz* 0 to 85 8 ld epsoic (pb-free) m8.15b isl6612aeib -40 to +85 8 ld epsoic m8.15b isl6612aeibz* -40 to +85 8 ld epsoic (pb-free) m8.15b ISL6612AEIR -40 to +85 8 ld epsoic m8.15b isl6612aib -40 to +85 8 ld soic m8.15 isl6612air -40 to +85 10 ld 3x3 dfn l10.3x3 isl6612airz* -40 to +85 10 ld 3x3 dfn (pb-free) l10.3x3 isl6613acb 0 to 85 8 ld soic m8.15 isl6613acbz* 0 to 85 8 ld soic (pb-free) m8.15 isl6613aecb 0 to 85 8 ld epsoic m8.15b isl6613aecbz* 0 to 85 8 ld epsoic (pb-free) m8.15b isl6613aeib -40 to +85 8 ld epsoic m8.15b isl6613aeibz* -40 to +85 8 ld epsoic (pb-free) m8.15b isl6613aeir -40 to +85 8 ld epsoic m8.15b isl6613acr 0 to 85 10 ld 3x3 dfn l10.3x3 isl6613acrz* 0 to 85 10 ld 3x3 dfn (pb-free) l10.3x3 isl6613aib -40 to +85 8 ld soic m8.15 isl6613air -40 to +85 10 ld 3x3 dfn l10.3x3 isl6613airz* -40 to +85 10 ld 3x3 dfn (pb-free) l10.3x3 *intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020c. ** add (-t) suffix for tape and reel. check website for availability. ordering information (continued) part number** temp. range (c) package pkg. dwg. # pinouts isl6612acb, isl6612aib, isl6613acb, isl6613aib (soic) isl6612aecb, isl6612aeib, ISL6612AEIR, isl6613aecb, isl6613aeib, isl6613aeir (epsoic) top view isl6612acr, isl6612air, isl6613acr, isl6613air (10l 3x3 dfn) top view ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase pvcc vcc lgate gnd 1 ugate boot n/c pwm phase pvcc n/c vcc 2 3 4 5 gnd 10 9 8 7 6 lgate gnd block diagram isl6612a and isl6613a pvcc vcc pwm +5v 10k 8k boot ugate phase lgate gnd for dfn and epsoic-devices, the pad on the bottom side of pad the package must be soldered to the circuit?s ground. uvcc = vcc for isl6612a control logic por/ shoot- through protection pre-por ovp (lvcc) uvcc = pvcc for isl6613a uvcc features otp and isl6612a, isl6613a
3 fn9159.2 january 4, 2005 typical application - 3 channel converte r using isl65xx and is l6612a gate drivers boot ugate phase lgate pwm pvcc +12v boot ugate phase lgate pwm pvcc vcc +12v boot ugate phase lgate pwm pvcc +12v +v core pgood vid fs gnd isen3 isen2 isen1 pwm3 pwm2 pwm1 vsen main vfb vcc +5v comp isl6612a control isl65xx vcc isl6612a vcc isl6612a gnd gnd gnd +5v to 12v +5v to 12v +5v to 12v isl6612a, isl6613a
4 fn9159.2 january 4, 2005 absolute maximum rati ngs thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v supply voltage (pvcc) . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.3v boot voltage (v boot ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36v input voltage (v pwm ) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 7v ugate. . . . . . . . . . . . . . . . . . . v phase - 0.3v dc to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v dc to v pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to v pvcc + 0.3v phase. . . . . . . . . . . . . . . gnd - 0.3v dc to 15v dc (v pvcc = 12v) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot-phase = 12v) esd rating human body model . . . . . . . . . . . . . . . . . . . . class i jedec std recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . .-40c to 85c maximum operating junction temperature . . . . . . . . . . . . . . 125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v 10% supply voltage range, pvcc . . . . . . . . . . . . . . . . 5v to 12v 10% thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 100 n/a epsoic package (notes 2, 3). . . . . . . 50 7 dfn package (notes 2, 3) . . . . . . . . . . 48 7 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effe ctive thermal conductivity test board in free air. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 4. guaranteed by design. not 100% tested in production. electrical specifications recommended operating conditions, unless otherwise noted. parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc isl6612a, f pwm = 300khz, v vcc =12v - 7.2 - ma isl6613a, f pwm = 300khz, v vcc =12v - 4.5 - ma i vcc isl6612a, f pwm = 1mhz, v vcc = 12v - 11 - ma isl6613a, f pwm = 1mhz, v vcc = 12v - 5 - ma gate drive bias current i pvcc isl6612a, f pwm = 300khz, v pvcc = 12v - 2.5 - ma isl6613a, f pwm = 300khz, v pvcc = 12v - 5.2 - ma i pvcc isl6612a, f pwm = 1mhz, v pvcc = 12v - 7 - ma isl6613a, f pwm = 1mhz, v pvcc = 12v - 13 - ma power-on reset and enable vcc rising threshold t a = 0c to 85c 9.35 9.80 10.00 v vcc rising threshold t a = -40c to 85c 8.35 9.80 10.00 v vcc falling threshold t a = 0c to 85c 7.35 7.60 8.00 v vcc falling threshold t a = -40c to 85c 6.35 7.60 8.00 v pwm input (see timing diagram on page 6) input current i pwm v pwm = 5v - 450 - a v pwm = 0v - -400 - a pwm rising threshold vcc = 12v - 3.00 - v pwm falling threshold vcc = 12v - 2.00 - v typical three-state shutdown window vcc = 12v 1.80 - 2.40 v three-state lower gate falling threshold vcc = 12v - 1.50 - v isl6612a, isl6613a
5 fn9159.2 january 4, 2005 three-state lower gate rising threshold vcc = 12v - 1.00 - v three-state upper gate rising threshold vcc = 12v - 3.20 - v three-state upper gate falling threshold vcc = 12v - 2.60 - v shutdown holdoff time t tsshd - 245 - ns ugate rise time t ru v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time t rl v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time t fu v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time t fl v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on propagation delay (note 4) t pdhu v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on propagation delay (note 4) t pdhl v pvcc = 12v, 3nf load, adaptive - 10 - ns ugate turn-off propagation delay (note 4) t pdlu v pvcc = 12v, 3nf load - 10 - ns lgate turn-off propagation delay (note 4) t pdll v pvcc = 12v, 3nf load - 10 - ns lg/ug three-state propagation delay (note 4) t pdts v pvcc = 12v, 3nf load - 10 - ns output upper drive source current (note 4) i u_source v pvcc = 12v, 3nf load - 1.25 - a upper drive source impedance r u_source 150ma source current 1.25 2.0 3.0 ? upper drive sink current (note 4) i u_sink v pvcc = 12v, 3nf load - 2 - a upper drive transition sink impedance (note 4) r u_sink_tr 70ns with respect to pwm falling - 1.3 2.2 ? upper drive dc sink impedance r u_sink_dc 150ma source current 0.9 1.65 3.0 ? lower drive source current (note 4) i l_source v pvcc = 12v, 3nf load - 2 - a lower drive source impedance r l_source 150ma source current 0.85 1.25 2.2 ? lower drive sink current (note 4) i l_sink v pvcc = 12v, 3nf load - 3 - a lower drive sink impedance r l_sink 150ma sink current 0.60 0.80 1.35 ? electrical specifications recommended operating conditions, unless otherwise noted. (continued) parameter symbol test conditions min typ max units functional pin description package pin # pin symbol function soic dfn 1 1 ugate upper gate drive output. connect to gate of high-side power n-channel mosfet. 2 2 boot floating bootstrap supply pin for the upper gate driv e. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see the internal bootstrap device section under description for guidance in choosing the capacitor value. - 3, 8 n/c no connection. 3 4 pwm the pwm signal is the control input for the driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section under description for further details. connect this pin to the pwm output of the controller. 4 5 gnd bias and reference ground. all signals are referenced to this node. it is also the power ground return of the driver. 5 6 lgate lower gate drive output. connect to gate of the low-side power n-channel mosfet. 6 7 vcc connect this pin to a +12v bias supply. place a high quality low esr cera mic capacitor from this pin to gnd. 7 9 pvcc this pin supplies power to both upper and lower gate dr ives in isl6613a; only the lower gate drive in isl6612a. its operating range is +5v to 12v. place a high quality low esr ceramic capacitor from this pin to gnd. 8 10 phase connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate drive. 9 11 pad connect this pad to the power ground plane (gnd) via thermally enhanced connection. isl6612a, isl6613a
6 fn9159.2 january 4, 2005 description operation designed for versatility and speed, the isl6612a and isl6613a mosfet drivers control both high-side and low- side n-channel fets of a half-bridge power train from one externally provided pwm signal. prior to vcc exceeding its por level, the pre-por overvoltage protection function is activated during initial startup; the upper gate (ugate) is held low and the lower gate (lgate), controlled by the pre-por overvoltage protection circuits, is connected to the phase. once the vcc voltage surpasses the vcc rising threshold (see electrical specifications), the pwm si gnal takes control of gate transitions. a rising edge on pwm initiates the turn-off of the lower mosfet (see timing diagram). after a short propagation delay [t pdll ], the lower gate begins to fall. typical fall times [t fl ] are provided in the elec trical specifications section. adaptive shoot-through circuitry monitors the phase voltage and determines the upper gate delay time [t pdhu ]. this prevents both the lower and upp er mosfets from conducting simultaneously. once this delay period is complete, the upper gate drive begins to rise [t ru ] and the upper mosfet turns on. a falling transition on pwm results in the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. again, the adaptive shoot-through circuitry determines the lower gate delay time, t pdhl . the phase voltage and the ugate voltage are monitored, and the lower gate is allowed to rise after phase drops below a level or the voltage of ugate to phase reaches a level depending upon the current direction (see next section for details). the lower gate then rises [t rl ], turning on the lower mosfet. advanced adaptive zero shoot-through deadtime control (patent pending) these drivers incorporate a uni que adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfets? body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lower mosfet, the phase voltage is monitored until it reaches a -0.2v/+0.8v trip point for a forward/reverse current, at which time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage preven ting from false detection of the -0.2v phase level during r ds(on conduction period. in the case of zero current, the ugate is re leased after 35ns delay of the lgate dropping below 0.5v. during the phase detection, the disturbance of lgate?s falling transition on the phase node is blanked out to prev ent falsely tripping. once the phase is high, the advanced adaptive shoot-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase falls to less than +0.8v, the lgate is released to turn on. three-state pwm input a unique feature of these driver s and other intersil drivers is the addition of a shutdown windo w to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. pwm ugate lgate t fl t pdhu t pdll t rl t tsshd t pdts t pdts 1.5v 7 fn9159.2 january 4, 2005 this feature helps prevent a ne gative transient on the output voltage when the output is s hut down, eliminating the schottky diode that is used in some systems for protecting the load from reversed output voltage events. in addition, more than 400mv hysteresis also incorporates into the three-state shutdown window to eliminate pwm input oscillations due to the capacitive load seen by the pwm input through the body diode of the controller?s pwm output when the power-up and/or power-down sequence of bias supplies of the driver and pwm controller are required. power-on reset (por) function during initial startup, the vcc voltage rise is monitored. once the rising vcc voltage exceeds 9.8v (typically), operation of the driver is enabled and the pwm input signal takes control of the gate drives. if vcc drops below the falling threshold of 7.6v (typica lly), operation of the driver is disabled. pre-por overvoltage protection prior to vcc exceeding its por level, the upper gate is held low and the lower gate is controlled by the overvoltage protection circuits during initial startup. the phase is connected to the gate of th e low side mosfet (lgate), which provides some protection to the microprocessor if the upper mosfet(s) is shorted during initial startup. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. when vcc drops below its por level, both gates pull low and the pre-por overvoltage protection circuits are not activated until vcc resets. internal bootstrap device both drivers feature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the boots trap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above uvcc + 5v and its capacitance value can be chosen from the following equation: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the ? v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. as an example, suppose two irlr7821 fets are chosen as the upper mosfets. the gate charge, q g , from the data sheet is 10nc at 4.5v (v gs ) gate-source voltage. then the q gate is calculated to be 53nc for uvcc (i.e. pvcc in isl6613a, vcc in isl6612a) = 12v. we will assume a 200mv droop in drive voltage over the pwm cycle. we find that a bootstrap capacitance of at least 0.267 f is required. gate drive voltage versatility the isl6612a and isl6613a provide the user flexibility in choosing the gate drive voltage for efficiency optimization. the isl6612a upper gate drive is fixed to vcc [+12v], but the lower drive rail can range from 12v down to 5v depending on what voltage is applied to pvcc. the isl6613a ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. power dissipation package power dissipation is mainly a function of the switching frequency (f sw ), the output drive impedance, the external gate resi stance, and the selected mosfet?s internal gate resistance and total gate charge. calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125c. the maximum allowable ic power dissipation for the so8 package is approximately 800mw at room temperature, while the power dissipation capa city in the epsoic and dfn packages, with an exposed heat escape pad, is more than 2w and 1.5w, respective ly. both epsoic and dfn packages are more suitable for high frequency applications. see layout considerations pa ragraph for thermal transfer improvement suggestions. when designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for c boot_cap q gate ? v boot_cap -------------------------------------- q gate q g1 uvcc ? v gs1 ----------------------------------- - n q1 ? = (eq. 1) 50nc 20nc figure 2. bootstrap capacitance vs boot ripple voltage ? v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1. 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc isl6612a, isl6613a
8 fn9159.2 january 4, 2005 the selected mosfets. the total gate drive power losses due to the gate charge of mosf ets and the driver?s internal circuitry and their corresponding average driver current can be estimated with equations 2 and 3, respectively, where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q is the driver?s total quiescent current with no l oad at both drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively; uvcc and lvcc are the drive voltages for both upper and lower fets, respectively. the i q* vcc product is the quiescent po wer of the driver without capacitive load and is typically 116mw at 300khz. the total gate drive power losses are dissipated among the resistive components along t he transition path. the drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of mosfets. figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. the power dissipation on the driver can be roughly estimated as: layout considerations for heat spreading, place copper underneath the ic whether it has an exposed pad or not. the copper area can be extended beyond the bottom area of the ic and/or connected to buried copper pl ane(s) with thermal vias. this combination of vias for vert ical heat escape, extended copper plane, and buried planes for heat spreading allows the ic to achieve its full thermal potential. place each channel power component as close to each other as possible to reduce pcb copper losses and pcb parasitics: shortest distance between drains of upper fets and sources of lower fets; shortest distance between drains of lower fets and the power ground. thus, smaller amplitudes of positive and negative ringing are on the switching edges of the phase node. however, some space in between the power components is required for good airflow. the traces from the drivers to the fets should be kept short and wide to reduce the inductance of the traces and to promote clean drive signals. p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 2) p qg_q1 q g1 uvcc 2 ? v gs1 --------------------------------------- f sw ? n q1 ? = p qg_q2 q g2 lvcc 2 ? v gs2 -------------------------------------- f sw ? n q2 ? = i dr q g1 uvcc n q1 ? ? v gs1 ----------------------------------------------------- - q g2 lvcc n q2 ? ? v gs2 ---------------------------------------------------- - + ?? ?? ?? f sw i q + ? = (eq. 3) p dr p dr_up p dr_low i q vcc ? ++ = (eq. 4) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 2 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = figure 3. typical upper-gate drive turn-on path figure 4. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase uvcc lvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 isl6612a, isl6613a
9 fn9159.2 january 4, 2005 isl6612a, isl6613a dual flat no-lead plastic package (dfn) d e a b 0.10 mc e 0.415 c section "c-c" nx (b) (a1) 2x c 0.15 0.15 2x b nx l ref. (nd-1)xe 5 a c (datum b) d2 d2/2 e2 e2/2 top view 7 bottom view 5 6 index area 8 ab nx k 6 index area (datum a) 12 n-1 n nx b 8 nx b nx l 0.200 c a seating plane 0.08 c a3 side view 0.10 c l10.3x3 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.23 0.28 5,8 d 3.00 bsc - d2 1.95 2.00 2.05 7,8 e 3.00 bsc - e2 1.55 1.60 1.65 7,8 e 0.50 bsc - k0.25 - - - l0.30 0.35 0.40 8 n102 nd 5 3 rev. 3 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. for odd terminal/side c l e terminal tip l c c
10 fn9159.2 january 4, 2005 isl6612a, isl6613a small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15b 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.056 0.066 1.43 1.68 - a1 0.001 0.005 0.03 0.13 - b 0.0138 0.0192 0.35 0.49 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.31 3.39 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.64 6 n8 87 0 o 8 o 0 o 8 o - p - 0.094 - 2.387 11 p1 - 0.094 - 2.387 11 rev. 2 11/03 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are s hown for reference only. 9. the lead width ?b?, as measur ed 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9159.2 january 4, 2005 isl6612a, isl6613a small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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